[PATCH] D121758: [clang-format] Add support for formatting Verilog code

[sstwcw via Phabricator via cfe-commits]

sstwcw added inline comments.


================
Comment at: clang/lib/Format/UnwrappedLineParser.cpp:534
         continue;
-      parseBlock(/*MustBeDeclaration=*/false, /*AddLevels=*/1u,
-                 /*MunchSemi=*/true, /*UnindentWhitesmithBraces=*/false,
-                 CanContainBracedList,
+      parseBlock(/*Flags=*/CanContainBracedList * BLOCK_CAN_CONTAIN_BRACED_LIST,
+                 /*AddLevels=*/1u,
----------------
One of the people in charge said multiplying with a boolean might trigger warnings.  Here I compiled with gcc.  This version doesn't trigger warnings.  The other way to do it, `CanContainBracedList ? BLOCK_CAN_CONTAIN_BRACED_LIST : 0`, triggers a warning that I shouldn't mix enum and integer.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121758/new/

https://reviews.llvm.org/D121758