[PATCH] D121758: [clang-format] Add support for formatting Verilog code

sstwcw via Phabricator via cfe-commits cfe-commits at lists.llvm.org
Tue Mar 15 16:33:47 PDT 2022


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Because Verilog uses the backtick instead of hash for preprocessor
directives, we replaced `is(tok::hash)` with a new function `isPPHash`.

`UnwrappedLineParser::parseBlock` has more flags, so we used a bit
field.

We need to lex the backtick, and the lexer had problems with that.  So
we modified how the lexer looks for whitespace.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D121758

Files:
  clang/docs/ClangFormatStyleOptions.rst
  clang/include/clang/Format/Format.h
  clang/lib/Format/ContinuationIndenter.cpp
  clang/lib/Format/Format.cpp
  clang/lib/Format/FormatToken.h
  clang/lib/Format/FormatTokenLexer.cpp
  clang/lib/Format/FormatTokenLexer.h
  clang/lib/Format/TokenAnnotator.cpp
  clang/lib/Format/TokenAnnotator.h
  clang/lib/Format/UnwrappedLineFormatter.cpp
  clang/lib/Format/UnwrappedLineParser.cpp
  clang/lib/Format/UnwrappedLineParser.h
  clang/lib/Format/WhitespaceManager.cpp
  clang/tools/clang-format/ClangFormat.cpp
  clang/unittests/Format/CMakeLists.txt
  clang/unittests/Format/FormatTestUtils.h
  clang/unittests/Format/FormatTestVerilog.cpp

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