[PATCH] D71124: [RISCV] support clang driver to select cpu

Kuan Hsu Chen (Zakk) via Phabricator via cfe-commits cfe-commits at lists.llvm.org
Tue Dec 10 06:57:03 PST 2019


khchen marked 3 inline comments as done.
khchen added inline comments.


================
Comment at: clang/lib/Basic/Targets/RISCV.cpp:164
+
+static constexpr llvm::StringLiteral ValidRV32CPUNames[] = {{"generic-rv32"},
+                                                            {"rocket-rv32"}};
----------------
lenary wrote:
> Is there not a tablegen'd implementation of these based on https://github.com/llvm/llvm-project/blob/master/llvm/lib/Target/RISCV/RISCV.td#L96-L99 (which will include `rocket-rv32` and `rocket-rv64` when those two schedules are landed)?
you are right, if generic-cpu uses rocket chip scheduler, it's okay to abandon this patch.

 


================
Comment at: clang/lib/Basic/Targets/RISCV.h:46
 
+  bool setCPU(const std::string &Name) override {
+    CPU = Name;
----------------
Jim wrote:
> I think this should test cpu name is valid first. And assign Name to CPU, if it is valid.
yes, you are right, thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71124/new/

https://reviews.llvm.org/D71124





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