[PATCH] D71124: [RISCV] support clang driver to select cpu

[Kuan Hsu Chen (Zakk) via Phabricator via cfe-commits]

khchen updated this revision to Diff 233082.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71124/new/

https://reviews.llvm.org/D71124

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/riscv-cpus.c


Index: clang/test/Driver/riscv-cpus.c
===================================================================
--- /dev/null
+++ clang/test/Driver/riscv-cpus.c
@@ -0,0 +1,8 @@
+// Check target CPUs are correctly passed.
+
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rocket-rv32 | FileCheck -check-prefix=ROCKETCHIP32 %s
+// ROCKETCHIP32: "-fuse-init-array" "-target-cpu" "rocket-rv32"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=rocket-rv64 | FileCheck -check-prefix=ROCKETCHIP64 %s
+// ROCKETCHIP64: "-fuse-init-array" "-target-cpu" "rocket-rv64"
+
Index: clang/lib/Driver/ToolChains/CommonArgs.cpp
===================================================================
--- clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -304,6 +304,11 @@
     }
     return TargetCPUName;
   }
+  case llvm::Triple::riscv32:
+  case llvm::Triple::riscv64:
+    if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ))
+      return A->getValue();
+    return "";
 
   case llvm::Triple::bpfel:
   case llvm::Triple::bpfeb:
Index: clang/lib/Basic/Targets/RISCV.h
===================================================================
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -24,7 +24,7 @@
 // RISC-V Target
 class RISCVTargetInfo : public TargetInfo {
 protected:
-  std::string ABI;
+  std::string ABI, CPU;
   bool HasM;
   bool HasA;
   bool HasF;
@@ -43,6 +43,13 @@
     WIntType = UnsignedInt;
   }
 
+  bool setCPU(const std::string &Name) override {
+    if (!isValidCPUName(Name))
+      return false;
+    CPU = Name;
+    return true;
+  }
+
   StringRef getABI() const override { return ABI; }
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override;
@@ -94,6 +101,7 @@
     return false;
   }
 
+  bool isValidCPUName(StringRef Name) const override;
   void setMaxAtomicWidth() override {
     MaxAtomicPromoteWidth = 128;
 
@@ -118,6 +126,7 @@
     return false;
   }
 
+  bool isValidCPUName(StringRef Name) const override;
   void setMaxAtomicWidth() override {
     MaxAtomicPromoteWidth = 128;
 
Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -160,3 +160,17 @@
 
   return true;
 }
+
+static constexpr llvm::StringLiteral ValidRV32CPUNames[] = {{"generic-rv32"},
+                                                            {"rocket-rv32"}};
+
+bool RISCV32TargetInfo::isValidCPUName(StringRef Name) const {
+  return llvm::find(ValidRV32CPUNames, Name) != std::end(ValidRV32CPUNames);
+}
+
+static constexpr llvm::StringLiteral ValidRV64CPUNames[] = {{"generic-rv64"},
+                                                            {"rocket-rv64"}};
+
+bool RISCV64TargetInfo::isValidCPUName(StringRef Name) const {
+  return llvm::find(ValidRV64CPUNames, Name) != std::end(ValidRV64CPUNames);
+}


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