[PATCH] D71124: [RISCV] support clang driver to select cpu

[Sam Elliott via Phabricator via cfe-commits]

lenary added inline comments.


================
Comment at: clang/lib/Basic/Targets/RISCV.cpp:164
+
+static constexpr llvm::StringLiteral ValidRV32CPUNames[] = {{"generic-rv32"},
+                                                            {"rocket-rv32"}};
----------------
khchen wrote:
> lenary wrote:
> > Is there not a tablegen'd implementation of these based on https://github.com/llvm/llvm-project/blob/master/llvm/lib/Target/RISCV/RISCV.td#L96-L99 (which will include `rocket-rv32` and `rocket-rv64` when those two schedules are landed)?
> you are right, if generic-cpu uses rocket chip scheduler, it's okay to abandon this patch.
> 
>  
No, that's not quite what I mean. When we add the rocket schedules, there will be additional `ProcessorModel` entries for the rocket chips, in addition to the current generic models. 

The point in these `ProcessorModel` entries is if a user passes `-mcpu=generic-rv64`, then `[Feature64Bit, FeatureRVCHints]` will get turned on, because they chose a specific cpu. This is different to validating that the correct features are enabled in order to choose a cpu, which seems the correct way around.

Then instead of checking against hard-coded lists, you use use `MCSubtargetInfo::isCPUStringValid(StringRef)`, which uses the info from the `ProcessorModel` tablegen entries. 


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D71124/new/

https://reviews.llvm.org/D71124