[all-commits] [llvm/llvm-project] ef067f: [AMDGPU][SIInsertWaitcnts] Do not add s_waitcnt wh...

[Pierre van Houtryve via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ef067f52044042fbe1b6fa21a90bfdbcf1622b02
      https://github.com/llvm/llvm-project/commit/ef067f52044042fbe1b6fa21a90bfdbcf1622b02
  Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
  Date:   2023-12-15 (Fri, 15 Dec 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
    M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
    M llvm/lib/Target/AMDGPU/SOPInstructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
    M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
    M llvm/test/CodeGen/AMDGPU/atomicrmw-nand.ll
    M llvm/test/CodeGen/AMDGPU/back-off-barrier-subtarget-feature.ll
    M llvm/test/CodeGen/AMDGPU/fence-barrier.ll
    M llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics_i32_system.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
    M llvm/test/CodeGen/AMDGPU/force-store-sc0-sc1.ll
    M llvm/test/CodeGen/AMDGPU/fp-atomics-gfx940.ll
    M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/gds-allocation.ll
    M llvm/test/CodeGen/AMDGPU/global-atomics-fp-wrong-subtarget.ll
    M llvm/test/CodeGen/AMDGPU/global-atomics-fp.ll
    M llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
    M llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll
    M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
    M llvm/test/CodeGen/AMDGPU/global-saddr-store.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
    M llvm/test/CodeGen/AMDGPU/idemponent-atomics.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
    M llvm/test/CodeGen/AMDGPU/local-atomics-fp.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir
    M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
    A llvm/test/CodeGen/AMDGPU/preserve-user-waitcnt.ll
    M llvm/test/CodeGen/AMDGPU/release-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/shl_add_ptr_global.ll
    M llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
    M llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting-vscnt.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.mir

  Log Message:
  -----------
  [AMDGPU][SIInsertWaitcnts] Do not add s_waitcnt when the counters are known to be 0 already (#72830)

Co-authored-by: Juan Manuel MARTINEZ CAAMAÑO <juamarti at amd.com>