[all-commits] [llvm/llvm-project] f643ee: [mlir][vector] Add emulation patterns for vector m...

[Hsiangkai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f643eec892954653b1c9bde42407560caf660b8b
      https://github.com/llvm/llvm-project/commit/f643eec892954653b1c9bde42407560caf660b8b
  Author: Hsiangkai Wang <hsiangkai.wang at arm.com>
  Date:   2023-12-15 (Fri, 15 Dec 2023)

  Changed paths:
    M mlir/include/mlir/Dialect/Vector/Transforms/LoweringPatterns.h
    M mlir/lib/Dialect/Vector/Transforms/CMakeLists.txt
    A mlir/lib/Dialect/Vector/Transforms/VectorEmulateMaskedLoadStore.cpp
    A mlir/test/Dialect/Vector/vector-emulate-masked-load-store.mlir
    M mlir/test/lib/Dialect/Vector/TestVectorTransforms.cpp

  Log Message:
  -----------
  [mlir][vector] Add emulation patterns for vector masked load/store (#74834)

In this patch, it will convert

```
vector.maskedload %base[%idx_0, %idx_1], %mask, %pass_thru
```

to

```
%ivalue = %pass_thru
%m = vector.extract %mask[0]
%result0 = scf.if %m {
  %v = memref.load %base[%idx_0, %idx_1]
  %combined = vector.insert %v, %ivalue[0]
  scf.yield %combined
} else {
  scf.yield %ivalue
}
%m = vector.extract %mask[1]
%result1 = scf.if %m {
  %v = memref.load %base[%idx_0, %idx_1 + 1]
  %combined = vector.insert %v, %result0[1]
  scf.yield %combined
} else {
  scf.yield %result0
}
...
```

It will convert

```
vector.maskedstore %base[%idx_0, %idx_1], %mask, %value
```

to

```
%m = vector.extract %mask[0]
scf.if %m {
  %extracted = vector.extract %value[0]
  memref.store %extracted, %base[%idx_0, %idx_1]
}
%m = vector.extract %mask[1]
scf.if %m {
  %extracted = vector.extract %value[1]
  memref.store %extracted, %base[%idx_0, %idx_1 + 1]
}
...
```