[all-commits] [llvm/llvm-project] ff2622: [RISCV] Optimize gather/scatter to unit-stride mem...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ff2622b5ac6befc1f0814f83dabed8c04d7215ef
      https://github.com/llvm/llvm-project/commit/ff2622b5ac6befc1f0814f83dabed8c04d7215ef
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-09-15 (Fri, 15 Sep 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

  Log Message:
  -----------
  [RISCV] Optimize gather/scatter to unit-stride memop + shuffle (#66279)

If we have a gather or a scatter whose index describes a permutation of the
lanes, we can lower this as a shuffle + a unit strided memory operation.  For
RISCV, this replaces a indexed load/store with a unit strided memory operation
and a vrgather (at worst).

I did not bother to implement the vp.scatter and vp.gather variants of these
transforms because they'd only be legal when EVL was VLMAX.  Given that, they
should have been transformed to the non-vp variants anyways.  I haven't checked
to see if they actually are.