[all-commits] [llvm/llvm-project] d056d5: [RISCV] Use custom isel for vector indexed load/st...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d056d5decfb593cfc53b421a89075d2063f76ec9
      https://github.com/llvm/llvm-project/commit/d056d5decfb593cfc53b421a89075d2063f76ec9
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-19 (Fri, 19 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  Log Message:
  -----------
  [RISCV] Use custom isel for vector indexed load/store intrinsics.

There are many legal combinations of index and data VTs supported
for these intrinsics. This results in a lot of isel patterns in
RISCVGenDAGISel.inc.

By adding a separate table similar to what we use for segment
load/stores, we can more efficiently manually select these
intrinsics. We should also be able to reuse this table scalable
vector gather/scatter.

This reduces the llc binary size by ~56K.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D97033