[all-commits] [llvm/llvm-project] 98dff5: [RISCV] Move SHFLI matching to DAG combine. Add 32...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 98dff5e804229d1d2fc139e44e7a04fc06bb6f92
      https://github.com/llvm/llvm-project/commit/98dff5e804229d1d2fc139e44e7a04fc06bb6f92
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-19 (Fri, 19 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoB.td
    M llvm/test/CodeGen/RISCV/rv64Zbp.ll

  Log Message:
  -----------
  [RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64

We previously used isel patterns for this, but that used quite
a bit of space in the isel table due to OR being associative
and commutative. It also wouldn't handle shifts/ands being in
reversed order.

This generalizes the shift/and matching from GREVI to
take the expected mask table as input so we can reuse it for
SHFLI.

There is no SHFLIW instruction, but we can promote a 32-bit
SHFLI to i64 on RV64. As long as bit 4 of the control bit isn't
set, a 64-bit SHFLI will preserve 33 sign bits if the input had
at least 33 sign bits. ComputeNumSignBits has been updated to
account for that to avoid sext.w in the tests.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D96661


  Commit: dbf910f0d95011e9485af859a10efb75bf28ee89
      https://github.com/llvm/llvm-project/commit/dbf910f0d95011e9485af859a10efb75bf28ee89
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-19 (Fri, 19 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    A llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

  Log Message:
  -----------
  [RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics.

Just like we do for isel patterns, we need to call selectVLOp
to prevent 0 from being selected to X0 by the default isel.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D97021


Compare: https://github.com/llvm/llvm-project/compare/4ffad1fb489f...dbf910f0d950