[all-commits] [llvm/llvm-project] 7f5b38: [RISCV] Remove unneeded indexed segment load/store...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7f5b3886e41ca0ff9e4275e515bd6dde576ead35
      https://github.com/llvm/llvm-project/commit/7f5b3886e41ca0ff9e4275e515bd6dde576ead35
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-19 (Fri, 19 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  Log Message:
  -----------
  [RISCV] Remove unneeded indexed segment load/store vector pseudo instruction.

We had more combinations of data and index lmuls than we needed.

Also add some asserts to verify that the IndexVT and data VT have
the same element count when we isel these pseudo instructions.