[all-commits] [llvm/llvm-project] c7dd92: [RISCV] Support isel of scalable vector bitcasts

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c7dd92e8a590cd456b4daad87af9d3b746d05ca6
      https://github.com/llvm/llvm-project/commit/c7dd92e8a590cd456b4daad87af9d3b746d05ca6
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-18 (Thu, 18 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat-rv32.ll

  Log Message:
  -----------
  [RISCV] Support isel of scalable vector bitcasts

These should be NOPs so we can just replace with the input. This
matches what SVE does with isel patterns for all permutations.
Custom isel saves us from having to list all permurations for
all LMULs.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D96921