[all-commits] [llvm/llvm-project] 792627: [RISCV] Add support for fixed vector sign/zero ext...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 792627be359e5d3386c4d8bb97eb1e5e5ec43b0c
      https://github.com/llvm/llvm-project/commit/792627be359e5d3386c4d8bb97eb1e5e5ec43b0c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-02-18 (Thu, 18 Feb 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll

  Log Message:
  -----------
  [RISCV] Add support for fixed vector sign/zero extend from mask types.

Due to vXi64 on RV32, I've directly emitted this using _VL ISD
opcodes. If it wasn't for that we could just use fixed vector
BUILD_VECTOR and VSELECT and let those each be legalized.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D96910