[Mlir-commits] [mlir] [mlir][AMX] Memory effects to amx.tile_zero (PR #155403)

[Arun Thangamani]

arun-thmn wrote:

With `MemoryEffects<[MemWrite]` the `CSE` is restricted even for `reads` - I guess. For the below example, `%0` and `%1` doesn't get `CSE` to one `amx.tile_zero`. Now, I'm not very sure that  `MemoryEffects<[MemWrite]` can be a valid fix.
 
Example:
`%alloca = memref.alloca() : memref<16x32xf32>`
`%0 = amx.tile_zero : !amx.tile<16x16xf32>`
`%1 = amx.tile_zero : !amx.tile<16x16xf32>`
`amx.tile_store %alloca[%c0, %c0], %0 : memref<16x32xf32>, !amx.tile<16x16xf32>`
`amx.tile_store %alloca[%c0, %c16], %1 : memref<16x32xf32>, !amx.tile<16x16xf32>`


https://github.com/llvm/llvm-project/pull/155403