[Mlir-commits] [mlir] [mlir][AMX] Memory effects to amx.tile_zero (PR #155403)

[Adam Siemieniuk]

adam-smnk wrote:

> With `MemoryEffects<[MemWrite]` the `CSE` is restricted even for `reads` - I guess. 

Good 👍

> For the below example, `%0` and `%1` doesn't get `CSE` to one `amx.tile_zero`. Now, I'm not very sure that `MemoryEffects<[MemWrite]` can be a valid fix.
> 
> Example: `%alloca = memref.alloca() : memref<16x32xf32>` `%0 = amx.tile_zero : !amx.tile<16x16xf32>` `%1 = amx.tile_zero : !amx.tile<16x16xf32>` `amx.tile_store %alloca[%c0, %c0], %0 : memref<16x32xf32>, !amx.tile<16x16xf32>` `amx.tile_store %alloca[%c0, %c16], %1 : memref<16x32xf32>, !amx.tile<16x16xf32>`

I think it is in line with the updated semantics we want to achieve. Each tile load/zero serves as a hint to use a separate tile register. User will have to be a bit more deliberate when creating AMX ops and not rely as much on an automatic cleanup.

I'd suggest to move forward with `MemWrite` to model side effects of tile zero and load.
Please also update op descriptions to explain the new intended behavior/usage.

https://github.com/llvm/llvm-project/pull/155403