[llvm-dev] Question about registers and subregisters

[Quentin Colombet via llvm-dev]

Hi Francesco,

Yes, the subreg are transitive but the transitivity may not be represented the way you expect.

Essentially all the registers map to a set of register units. Two registers overlap if their register units overlap.
The register units are not necessarily actual register.

E.g., in your first example, ABCD maps to the reg unit A, B, C, and D.
In your second example, ADE maps to A and AD maps to A as well. Assuming D and E are not physically accessible by themselves.

You can take query the regunits using the related MCRegisterInfo API, e.g., MCRegUnitIterator.

Hope this helps.

Cheers,
-Quentin

> On Sep 17, 2021, at 11:19 AM, Francesco Bertolaccini via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> 
> Is the relation between registers and their subregisters transitive?
> That is, supposing I have registers
> 
>  ABCD
>  ABC
>  AB
>  A
> 
> such that ABCD has subregister ABC, ABC has subregister AB and AB has
> subregister A. Does LLVM recognize that A is also a subregister of ABCD?
> 
> Also, suppose now that my registers are
> 
>  ABC
>  ADE
>  AB
>  AD
>  A
> 
> with a relationship similar to the one described above, such that ABC
> and ADE are not in any kind of register-subregister relationship but
> still partially overlap. Is LLVM able to recognize this, and treat the
> situation accordingly (when spilling, etc)?
> 
> Thanks,
> Francesco
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