[llvm-dev] Question about registers and subregisters

[Francesco Bertolaccini via llvm-dev]

Thanks Quentin, it does help!
I'm referring to the docs at
https://llvm.org/docs/WritingAnLLVMBackend.html#register-set-and-register-classes

How do register units play into the registers/register classes/register
sets described there?

The situation I mentioned in my original mail would be implemented
something like this, if I am not mistaken:

def A : Register<"A">;
def AB : Register<"AB"> {
  let SubRegs = [ A ];
};
def ABC : Register<"ABC"> {
  let SubRegs = [ AB ];
};
def ABCD : Register<"ABCD"> {
  let SubRegs = [ ABC ];
};

Are the underlying register units automagically generated by TableGen?

Best regards,
Francesco

On 17/09/2021 20:39, Quentin Colombet wrote:
> Hi Francesco,
> 
> Yes, the subreg are transitive but the transitivity may not be
> represented the way you expect.
> 
> Essentially all the registers map to a set of register units. Two
> registers overlap if their register units overlap.
> The register units are not necessarily actual register.
> 
> E.g., in your first example, ABCD maps to the reg unit A, B, C, and D.
> In your second example, ADE maps to A and AD maps to A as well. Assuming
> D and E are not physically accessible by themselves.
> 
> You can take query the regunits using the related MCRegisterInfo API,
> e.g., MCRegUnitIterator.
> 
> Hope this helps.
> 
> Cheers,
> -Quentin
>