[llvm-dev] Question about registers and subregisters

[Francesco Bertolaccini via llvm-dev]

Is the relation between registers and their subregisters transitive?
That is, supposing I have registers

  ABCD
  ABC
  AB
  A

such that ABCD has subregister ABC, ABC has subregister AB and AB has
subregister A. Does LLVM recognize that A is also a subregister of ABCD?

Also, suppose now that my registers are

  ABC
  ADE
  AB
  AD
  A

with a relationship similar to the one described above, such that ABC
and ADE are not in any kind of register-subregister relationship but
still partially overlap. Is LLVM able to recognize this, and treat the
situation accordingly (when spilling, etc)?

Thanks,
Francesco