[llvm-dev] Help: A Question about AArch64 Register Class

Ben Shi via llvm-dev llvm-dev at lists.llvm.org
Sun Oct 3 07:45:47 PDT 2021


I am modifying the new committed pass "aarch64-mi-peephole-opt", but get unexpected errors.

My code:

  const TargetRegisterClass *RC =

      (RegSize == 32) ? &AArch64::GPR32spRegClass : &AArch64::GPR64spRegClass;

  Register DstReg = MI.getOperand(0).getReg();

  Register SrcReg = MI.getOperand(1).getReg();

  Register TmpReg = MRI->createVirtualRegister(RC);

  BuildMI(*MBB, MI, DL, TII->get(AArch64::SUBXri), TmpReg)





But when I tried to compile a simple function with

"llc a.ll -mtriple=aarch64 -verify-machineinstrs", I got errors like


*** Bad machine code: Illegal virtual register for instruction ***

- function:    add_two_parts_imm_i64

- basic block: %bb.0  (0x561f681b0410)

- instruction: %3:gpr64common = SUBXri %0:gpr64, 2730, 12

- operand 1:   %0:gpr64

Expected a GPR64sp register, but got a GPR64 register

LLVM ERROR: Found 1 machine code errors.


But if I changed to Opcode from SUBXri to ANDXri, then the errors were eliminated.


What is difference between ANDXri and SUBXri? (also ADDXri has the same errors)

What should I do to avoid the errors with Opcode SUBXri/ADDXri ?


Ben Shi


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