[llvm-dev] What's SEXT_INREG and why DAGCombiner is producing it?

[Zhang via llvm-dev]

Hi:
In my toy compiler backend, I currently don't / won't support SEXT_IN_REG, mostly due to the lack of documentation explains its difference between the "normal" sext.


However, when compiling a test program, I notice the following messaging emitted by llc, despite already called ``setOperationType() to Expand``:


```
Combining: t41: i32 = sra t40, Constant:i64<31>, .\examples\crc.c:72:12
Creating new node: t44: i32 = sign_extend_inreg t2, ValueType:ch:i1, .\examples\crc.c:72:12
 ... into: t44: i32 = sign_extend_inreg t2, ValueType:ch:i1, .\examples\crc.c:72:12

```


I was under the impression the setOperationType(....EXPAND) call should instruct the ISel System to expand this DAG Node?
Another question would be, what's the correct semantic for SEXT_IN_REG? Can I just  implement it as SExt?




Zhang
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