[llvm-dev] What's SEXT_INREG and why DAGCombiner is producing it?

[Tim Northover via llvm-dev]

On Fri, 3 Dec 2021 at 04:07, Zhang via llvm-dev <llvm-dev at lists.llvm.org> wrote:
> In my toy compiler backend, I currently don't / won't support SEXT_IN_REG, mostly due to the lack of documentation explains its difference between the "normal" sext.

It's necessary/beneficial for sign extensions in types that aren't
legal on the target. For example most RISC backends have i32 and maybe
i64 as legal, so there's no other single-instruction way to represent
sign extensions from i8 or i16 (zero extension can be mapped to an
AND, though even it has a vector inreg form).

> However, when compiling a test program, I notice the following messaging emitted by llc, despite already called ``setOperationType() to Expand``:

The code seems to be in DAGCombiner.cpp line7518 (in visitSRA). It
looks like it checks legality to me, but in an early phase (before
legalization) might produce it anyway expecting it to be further
lowered later.

> Another question would be, what's the correct semantic for SEXT_IN_REG? Can I just  implement it as SExt?

Yes, it's just just a normal sign extend operation.

Cheers.

Tim.

>
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> Zhang
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