[llvm-dev] LLVM Weekly - #379, April 5th 2021

[Alex Bradbury via llvm-dev]

LLVM Weekly - #379, April 5th 2021
==================================

If you prefer, you can read a HTML version of this email at
<http://llvmweekly.org/issue/379>.

Welcome to the three hundred and seventy-ninth issue of LLVM Weekly, a weekly
newsletter (published every Monday) covering developments in LLVM, Clang, and
related projects. LLVM Weekly is brought to you by [Alex
Bradbury](https://www.linkedin.com/in/alex-bradbury/). Subscribe to future
issues at <http://llvmweekly.org> and pass it on to anyone else you think may
be interested. Please send any tips or feedback to <asb at asbradbury.org>, or
@llvmweekly or @asbradbury on Twitter.


## News and articles from around the web

The Women in Compilers and Tools Meetup Series [has been announced on the LLVM
blog](https://blog.llvm.org/posts/2021-03-31-womenincompilerstoolsmeetup/).
The virtual event will take place each month, featuring talks, tutorials, and
mentoring events.

Oleksandr Koval has posted an incredibly detailed blog post [listing all C++20
core language features with
examples](https://oleksandrkvl.github.io/2021/04/02/cpp-20-overview.html).


## On the mailing lists

* Vineet Kumar posted an RFC on [vector predication intrinsics support for the
  loop
  vectoriser](https://lists.llvm.org/pipermail/llvm-dev/2021-April/149580.html).

* LLVM GPU News issue #9 [is now
  available](https://lists.llvm.org/pipermail/llvm-dev/2021-April/149587.html).

* Andrew Safronov provided an update on [patches under review for the
  Tensilica Xtensa
  backend](https://lists.llvm.org/pipermail/llvm-dev/2021-April/149582.html).

* Sameer Sahasrabuddhe reignited discussion on the RFC thread on [abstracting
  over SSA IRs to implement generic
  analyses](https://lists.llvm.org/pipermail/llvm-dev/2021-March/149523.html).

* Kai Wang provided an updated on the RFC to [permit load/store/alloca for
  structs containing all scalable
  vectors](https://lists.llvm.org/pipermail/llvm-dev/2021-March/149518.html)
  and is still seeking feedback.

* Alex Bradbury is [polling for input from people who find the timing of the
  current biweekly RISC-V LLVM sync-up
  difficult](https://lists.llvm.org/pipermail/llvm-dev/2021-April/149573.html).


## LLVM commits

* The TargetRegisterInfo stack realignment functions were reorganised into
  shouldRealignStack, canRealignStack, and hasStackRealignment.
  [a9968c0](https://reviews.llvm.org/rGa9968c0a339a).

* TableGen now supports the 'assert' statement in class definitions.
  [5f473a0](https://reviews.llvm.org/rG5f473a04af91).

* The standard pass pipeline was updated to run an additional LICM
  (loop-invariant code motion) pass before LoopRotate.
  [a26f1bf](https://reviews.llvm.org/rGa26f1bf67ec7).

* The initial framework for a "context-sensitive global pre-inliner" was
  introduced. [30b0232](https://reviews.llvm.org/rG30b023233696).

* ORC is now the default JIT engine for LLI.
  [c42c67a](https://reviews.llvm.org/rGc42c67ad6044).

* For RISC-V, f16 values are passed in the lower 16-bits of an f32 when the F
  extension is enabled but Zfh is not, and the softPromoteHalf legalisation
  strategy is used. [a33fcaf](https://reviews.llvm.org/rGa33fcafaf049),
  [dbbc95e](https://reviews.llvm.org/rGdbbc95e3e5aa).

* Materialisation for 64-bit immediates on RV64 was improved.
  [d61b40e](https://reviews.llvm.org/rGd61b40ed2750),
  [d7ffa82](https://reviews.llvm.org/rGd7ffa82a8e62).


## Clang commits

* Support was added for C++2b's `size_t` literals.
  [dc7ebd2](https://reviews.llvm.org/rGdc7ebd2cb0cf).

* A new mechanism was added to allow tablegen to be used to indicate that
  groups of attributes are mutually exclusive.
  [4be8a26](https://reviews.llvm.org/rG4be8a26951da).

* Initial support was added for the OpenMP 5.1 dispatch directive and the
  novariants clause. [b7899ba](https://reviews.llvm.org/rGb7899ba0e8b7),
  [cb424fe](https://reviews.llvm.org/rGcb424fee3d6b).


## Other project commits

* Flang gained implementations of numeric instruction functions and reductions
  in its runtime. [5f6c5c6](https://reviews.llvm.org/rG5f6c5c63c7c2),
  [e372e0f](https://reviews.llvm.org/rGe372e0f90619).

* Linux/mips debugging support was removed from LLDB.
  [ce03a86](https://reviews.llvm.org/rGce03a862372a).

* Interactive trace start and stop methods were implemented, as part of work
  to support Intel Processor Trace in LLDB.
  [0b69756](https://reviews.llvm.org/rG0b69756110db).