[llvm-dev] [RFC] Tensilica Xtensa (ESP32) backend

[Andrei Safronov via llvm-dev]

Dear LLVM Community,

A few weeks ago, I published updated patches of the Xtensa Architecture backend for review. During this time, the 2nd patch was approved, and I am very happy about it .
Current situation is that first three patches are approved:

1. Recognize Xtensa in triple parsing code https://reviews.llvm.org/D64826 .
2. Add Xtensa ELF definitions https://reviews.llvm.org/D64827 .
3. Initial version of the Xtensa backend https://reviews.llvm.org/D64829 .

And the last seven patches not yet have been reviewed.
 I would like to ask everyone to help with reviewing following patches.

4. Add basic *.td files with Xtensa architecture description https://reviews.llvm.org/D64830 .
5. Add Xtensa MCTargetDescr initial functionality https://reviews.llvm.org/D64831 .
6. Add Xtensa basic assembler parser https://reviews.llvm.org/D64832 .
7. Add Xtensa instruction printer https://reviews.llvm.org/D64833 .
8. Add support of the Xtensa shift / load / store / move and processor control instructions. https://reviews.llvm.org/D64834 .
9. Add basic support of Xtensa disassembler https://reviews.llvm.org/D64835 .
10. Add relaxations and fixups. Add rest part of Xtensa Core Instructions. https://reviews.llvm.org/D64836 .

 I would be glad to receive any comments or feedback about them.

Thanks to all! Best regards,
Andrei Safronov

________________________________
From: Andrei Safronov
Sent: Wednesday, March 10, 2021 4:29 AM
To: llvm-dev at lists.llvm.org <llvm-dev at lists.llvm.org>
Subject: [llvm-dev] [RFC] Tensilica Xtensa (ESP32) backend

Hi All!

On behalf of Espressif Systems, I would like to propose Xtensa backend to be added as an experimental to LLVM project.

The new target should satisfy common rules (https://llvm.org/docs/DeveloperPolicy.html#adding-a-new-target) to be upstreamed in experimental mode.
Therefore, we prepared an overview about conformance of the Xtensa backend to these rules:

1. Every target must have a code owner.
  I added myself in CODE_OWNERS.txt as responsible for Xtensa backend support in the first patch.

2. There must be an active community behind the target.
  We have been developing the Xtensa backend project for 3 years, the latest version is ported to LLVM release 11.0.0.
  https://github.com/espressif/llvm-project . The Xtensa backend project now implements object code generation, architecture-dependent optimizations and it became possible to use clang to compile software projects for the EPSP32 / ESP8266 processor family.

3. The code must be free of contentious issues.
  The Xtensa backend code deisgned with minimum changes in IR behaviour.

4. The code conforms to all of the policies laid out in this developer policy document, including license, patent, and coding standards.
  We paid attention to all these requirements in code design.

5. The target should have either reasonable documentation on how it works (ISA, ABI, etc.) or a publicly available simulator/hardware (either free or cheap enough) - preferably both.
  The Xtensa target is implemented in Qemu emulator https://github.com/qemu/qemu/tree/master/target/xtensa and has publicly available hardware implementations, for example ESP32/ESP8266 MCU's family https://www.espressif.com/en/products/socs/esp32 .  We also created the Xtensa ISA documentation project https://github.com/espressif/xtensa-isa-doc , which is designed to simplify the patch review process, this project is based on public sources.

Some time ago, we already presented this project for discussion to the LLVM community in a letter
https://lists.llvm.org/pipermail/llvm-dev/2019-March/130796.html , and published a series of patches in the Phabricator:

1. Recognize Xtensa in triple parsing code https://reviews.llvm.org/D64826 .
2. Add Xtensa ELF definitions https://reviews.llvm.org/D64827 .
3. Initial version of the Xtensa backend https://reviews.llvm.org/D64829 .
4. Add basic * td files with Xtensa architecture description https://reviews.llvm.org/D64830 .
5. Add Xtensa MCTargetDescr initial functionality https://reviews.llvm.org/D64831 .
6. Add Xtensa basic assembler parser https://reviews.llvm.org/D64832 .
7. Add Xtensa instruction printer https://reviews.llvm.org/D64833 .
8. Add support of the Xtensa shift / load / store / move and processor control instructions. https://reviews.llvm.org/D64834 .
9. Add basic support of Xtensa disassembler https://reviews.llvm.org/D64835 .
10. Add relaxations and fixups. Add rest part of Xtensa Core Instructions. https://reviews.llvm.org/D64836 .

Currently, patches 1 and 3 have been approved, but other patches are still waiting for review. The patches 1-10 in the Phabricator are updated in accordance with the latest LLVM API changes and comments from the patches review.

Now exists a strong demand and interest from our large developer community for LLVM Xtensa backend and there are also some other companies in a world which have Xtensa based chips. For example, Xtensa backend helps to implement Rust for the Xtensa https://github.com/MabezDev/rust-xtensa and TinyGo https://tinygo.org/faq/what-about-esp8266-esp32/ .

But for the further development of such projects, it would be much more convenient to have the Xtensa backend implementation in the main LLVM version.

So, it would be great if the LLVM community could help resume the review process.

All comments and suggestions are welcome!

Andrei Safronov
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