[llvm-dev] [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths

[David Greene via llvm-dev]

Chandler Carruth wrote:

> I strongly suspect that there remains widespread concern with the
> direction of this, I know I have them.
>
> I don't think that many of the people who have that concern have had
> time to come back to this RFC and make progress on it, likely because
> of other commitments or simply the amount of churn around SVE related
> patches and such. That is at least why I haven't had time to return to
> this RFC and try to write more detailed feedback.

We believe ARM SVE will be an important architecture going forward.  As
such, it's important to us that these questions and concerns get posted
and discussed, whatever the outcome may be.  If there are objections,
alternative proposals would be helpful.

I see a lot of SVE patches on Phab that are described as "not for
review."  I don't know how helpful that is.  It would be more helpful to
have actual patches intended for review/commit.  It is difficult to know
which is which in Phab.  Could patches not intended for review either be
removed if not needed, or their subjects updated to indicate they are
not for review but for discussion purposes so that it's easier to filter
search results?

                                  -David