[llvm-dev] [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
Graham Hunter via llvm-dev
llvm-dev at lists.llvm.org
Tue Jul 31 11:16:11 PDT 2018
Hi David,
> On 30 Jul 2018, at 18:37, David Greene via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
> Chandler Carruth wrote:
>
>> I strongly suspect that there remains widespread concern with the
>> direction of this, I know I have them.
>>
>> I don't think that many of the people who have that concern have had
>> time to come back to this RFC and make progress on it, likely because
>> of other commitments or simply the amount of churn around SVE related
>> patches and such. That is at least why I haven't had time to return to
>> this RFC and try to write more detailed feedback.
>
> We believe ARM SVE will be an important architecture going forward. As
> such, it's important to us that these questions and concerns get posted
> and discussed, whatever the outcome may be. If there are objections,
> alternative proposals would be helpful.
Yes, pointing out alternatives we've missed would be helpful.
> I see a lot of SVE patches on Phab that are described as "not for
> review." I don't know how helpful that is. It would be more helpful to
> have actual patches intended for review/commit. It is difficult to know
> which is which in Phab. Could patches not intended for review either be
> removed if not needed, or their subjects updated to indicate they are
> not for review but for discussion purposes so that it's easier to filter
> search results?
All 14 patches listed at the bottom of the RFC are ready for an initial round of review, so I'll change the descriptions tomorrow to indicate that. I'll check to see if I have any older ones lying around and abandon them if so.
-Graham
>
> -David
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