[llvm-dev] Pseudo-instruction that overwrites its input register

[Nemanja Ivanovic via llvm-dev]

This is typically accomplished with something like PPC's `RegConstraint`
and `NoEncode`. You can see examples of it that are very similar to what
you're after in PPC's load/store with update forms (i.e. load a value and
update the base register with the effective address - these are used for
pre-increment loads/stores).
For example: the definition of LBZU and friends in
lib/Target/PowerPC/PPCInstrInfo.td.
For a simpler example of just the `RegConstraint` usage (as it doesn't use
a compound node like PPC's address nodes), you can look at all the fused
multiply-add such as XSMADDADP in lib/Target/PowerPC/PPCInstrVSX.td.

Hope this helps.

On Sun, May 28, 2017 at 12:04 PM, Dr. ERDI Gergo via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

> On Sun, 28 May 2017, David Chisnall wrote:
>
>  let Constraints = "@earlyclobber $reg" in
>>>  def LDWRdPtr : Pseudo<(outs DREGS:$reg),
>>>                        (ins PTRREGS:$ptrreg),
>>>                        "ldw\t$reg, $ptrreg",
>>>                        [(set i16:$reg, (load i16:$ptrreg))]>,
>>>                 Requires<[HasSRAM]>;
>>>
>>> The problem, of course, is that with this definition I end up with code
>>> which assumes it is equivalent to save P before 'ldw r1:r2,P' or after. I
>>> tried adding "@earlyclobber $ptrreg" as a Constraint, but that just leads
>>> to an assertion failure during codegen (I assume because @earlyclobber is
>>> for output ports)
>>>
>>
>> You need to express the P as both an input and output operand and add a
>> constraint that both must be the same register.
>>
>
> OK, but then the pattern will have to include that extra output operand
> somehow, right? What would the pattern need to be so that during ISel, this
> LDWRdPtr instruction with the extra output still matches?
>
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