[llvm-dev] Pseudo-instruction that overwrites its input register

[Dr. ERDI Gergo via llvm-dev]

On Tue, 30 May 2017, Nemanja Ivanovic wrote:

> This is typically accomplished with something like PPC's `RegConstraint` and
> `NoEncode`. You can see examples of it that are very similar to what you're after in
> PPC's load/store with update forms (i.e. load a value and update the base register
> with the effective address - these are used for pre-increment loads/stores).
> For example: the definition of LBZU and friends in lib/Target/PowerPC/PPCInstrInfo.td.
> For a simpler example of just the `RegConstraint` usage (as it doesn't use a compound
> node like PPC's address nodes), you can look at all the fused multiply-add such as
> XSMADDADP in lib/Target/PowerPC/PPCInstrVSX.td.
> 
> Hope this helps.

Thanks!

However, none of the NoEncode examples in PPCInstrInfo.td seem to have an 
isel pattern; and the VSX examples, like XSMADDADP, seem to match on 
setting a single output:

   let BaseName = "XSMADDADP" in {
   let isCommutable = 1 in
   def XSMADDADP : XX3Form<60, 33,
                           (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
                           "xsmaddadp $XT, $XA, $XB", IIC_VecFP,
                           [(set f64:$XT, (fma f64:$XA, f64:$XB, f64:$XTi))]>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;

If I'm reading this right, this matches an instruction that updates $XT 
by taking the current $XT, and two extra args in $XA and $XB. However, my 
situation would be something akin to

(set f64:$XC, (fma f64:$XA, f64:$XB, f64:$XTi))

with the extra constraint that $XTi is overwritten in the process.

Is there maybe a way to write a pattern like

(set (tuple f64:$XC, f64:$XT), (fma f64:$XA, f64:$XB, f64:$XTi))

that would match

(set f64:$XC, (fma f64:$XA, f64:$XB, f64:$XTi))

by automatically lifting it to store $XT as well? (of course, with a 
RegConstraint that $XT = $XTi)