[llvm-dev] Pseudo-instruction that overwrites its input register

[Dr. ERDI Gergo via llvm-dev]

On Sun, 28 May 2017, David Chisnall wrote:

>>  let Constraints = "@earlyclobber $reg" in
>>  def LDWRdPtr : Pseudo<(outs DREGS:$reg),
>>                        (ins PTRREGS:$ptrreg),
>>                        "ldw\t$reg, $ptrreg",
>>                        [(set i16:$reg, (load i16:$ptrreg))]>,
>>                 Requires<[HasSRAM]>;
>>
>> The problem, of course, is that with this definition I end up with code which assumes it is equivalent to save P before 'ldw r1:r2,P' or after. I tried adding "@earlyclobber $ptrreg" as a Constraint, but that just leads to an assertion failure during codegen (I assume because @earlyclobber is for output ports)
>
> You need to express the P as both an input and output operand and add a constraint that both must be the same register.

OK, but then the pattern will have to include that extra output operand 
somehow, right? What would the pattern need to be so that during ISel, 
this LDWRdPtr instruction with the extra output still matches?