[llvm-dev] About CodeGen quality

[陳韋任 via llvm-dev]

>
> Our target doesn't support load i64, so we have following code
> in XXXISelLowering.cpp
>
>     setOperationAction(ISD::LOAD, MVT::i64, Custom);
>
> Transform load i64 to load v2i32 during type legalization.
>
>
> If misaligned load v2i32 isn't legal, don't generate it.  If it is legal,
> you might need to mess with your implementation of
> allowsMisalignedMemoryAccesses.
>
>
​Will check that. ​Just a little more explanation about the misaligned
part. We declare i64 is 8 align in the DataLayout, and in "%0 = load i64,
*i64 ptr, align 4" the alignment is 4. In the op legalization stage, it
will go through

    SelectionDAGLegalize::LegalizeLoadOps ->
TargetLowering::expandUnalignedLoad

We don't expect load i64 would be 4 align, so how do I know I will generate
misaligned load v2i32 beforehand? Another question is usually what we do to
handle load i64 if that is not natively supported? Is it correct
transforming load i64 to load v2i32? An existing backend example would be
great.

Besides of that, our target has bitset/bitextract instructions, we want to
> use them on bitfield
> access, too. But don't know how to do that.
>
>
> This is generally implemented by pattern-matching the shift and mask
> operations.  ARM has instructions like this if you're looking for
> inspiration; look for UBFX, SBFX and BFI.
>

​Thanks. Having example​ is good. :-)

Regards,
chenwj


-- 
Wei-Ren Chen (陳韋任)
Homepage: https://people.cs.nctu.edu.tw/~chenwj
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170616/5a4e9ebf/attachment.html>