[llvm-dev] About CodeGen quality

[Friedman, Eli via llvm-dev]

On 6/15/2017 4:06 AM, 陳韋任 via llvm-dev wrote:
> Hi Mats,
>
>   It's private backend. I will try describing what I am dealing with.
>
>     struct S {
>       unsigned int a : 8;
>       unsigned int b : 8;
>       unsigned int c : 8;
>       unsigned int d : 8;
>
>       unsigned int e;
>     }
>
> We want to read S->b for example. The size of struct S is 64 bits, and 
> seems LLVM treats it as i64.
> Below is the IR corresponding to S->b, IIRC.
>
>     %0 = load i64, *i64 ptr, align 4;
>     %1 = %0 lshr 8;
>     %2 = %1 and 255;

This looks fine.

>
> Our target doesn't support load i64, so we have following code 
> in XXXISelLowering.cpp
>
>   setOperationAction(ISD::LOAD, MVT::i64, Custom);
> Transform load i64 to load v2i32 during type legalization.

If misaligned load v2i32 isn't legal, don't generate it.  If it is 
legal, you might need to mess with your implementation of 
allowsMisalignedMemoryAccesses.

> Besides of that, our target has bitset/bitextract instructions, we 
> want to use them on bitfield
> access, too. But don't know how to do that.

This is generally implemented by pattern-matching the shift and mask 
operations.  ARM has instructions like this if you're looking for 
inspiration; look for UBFX, SBFX and BFI.

-Eli

-- 
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

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