[llvm-dev] Backend implementation of an architecture having only majority instructions

[Hal Finkel via llvm-dev]

On 06/03/2017 09:32 AM, Sreejita saha via llvm-dev wrote:
>
> Hello everyone,
>
> I was trying to create an LLVM backend for a processor with a very 
> simple architecture and that does all instructions like load, store, 
> arithmetic and logical instructions using a bunch of majority 
> functions. The processor has only one instruction(majority function) 
> in its ISA and breaks down all other instructions into a number of 
> majority instructions depending on what instruction it is. All the 
> instructions have different combinations of majority operations. Is 
> there any way to implement this without creating a new Selection DAG 
> node for the majority operation? Also can i create a selection DAG 
> node in the backend instruction info itself? If so then how?
>
> I was thinking of creation of a new Selection DAG node and mapping all 
> the other instructions like loads, stores as pseudo instructions and 
> breaking them up. Can someone please help me with this?
>

Why don't you just write TableGen patterns to match the various 
selection-DAG nodes onto the correct combinations of your instruction?

  -Hal

> Thanks!
>
> Sreejita
>
>
>
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-- 
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory

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