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<div class="moz-cite-prefix">On 06/03/2017 09:32 AM, Sreejita saha
via llvm-dev wrote:<br>
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cite="mid:CAMRe-mtttk43BROgFx2ryvuhOCeMaXPq2morkdUfS=wD1=cdMA@mail.gmail.com"
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<p style="font-family:sans-serif;font-size:13.696px"><span
style="font-size:13.696px">Hello everyone,</span><br>
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<p style="font-family:sans-serif;font-size:13.696px"> </p>
<p style="font-family:sans-serif;font-size:13.696px">I was
trying to create an LLVM backend for a processor with a very
simple architecture and that does all instructions like load,
store, arithmetic and logical instructions using a bunch of
majority functions. The processor has only one
instruction(majority function) in its ISA and breaks down all
other instructions into a number of majority instructions
depending on what instruction it is. All the instructions have
different combinations of majority operations. Is there any
way to implement this without creating a new Selection DAG
node for the majority operation? Also can i create a selection
DAG node in the backend instruction info itself? If so then
how?</p>
<p style="font-family:sans-serif;font-size:13.696px">I was
thinking of creation of a new Selection DAG node and mapping
all the other instructions like loads, stores as pseudo
instructions and breaking them up. Can someone please help me
with this?</p>
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Why don't you just write TableGen patterns to match the various
selection-DAG nodes onto the correct combinations of your
instruction?<br>
<br>
-Hal<br>
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<p style="font-family:sans-serif;font-size:13.696px"> </p>
<p style="font-family:sans-serif;font-size:13.696px">Thanks!</p>
<p style="font-family:sans-serif;font-size:13.696px">Sreejita</p>
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<pre class="moz-signature" cols="72">--
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory</pre>
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