[llvm-dev] Tablegen pattern matching question

[Bhatu via llvm-dev]

Hi all,

I want to match addition with 16bit integers. So I define a pattern
fragment as follows:
def simm16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;

Now I am confused between
(add R32:$dst, simm16:$im) and
(add R32:$dst, (i32 simm16:$im)).

Do both of them match the same pattern? Are they equivalent? If not what is
the difference?
I am also confused as to how ValueTypes relate to SDNodes as I think we are
able to use both of them as nodes.

-- 
Regards
Pratik Bhatu
Dual Degree(B.Tech + M.Tech), 5th Year
Computer Science and Engineering
IIT Hyderabad
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