[llvm-dev] Tablegen pattern matching question

[Ryan Taylor via llvm-dev]

What are you trying to add, I see you have a result $dst of register class
R32 and an imm src operand, what is being added? This looks more like a
move to me. And in the second example you are trying to force simm16:$I'm
to i32?

-Ryan

On Tue, Aug 30, 2016 at 1:21 PM, Bhatu via llvm-dev <llvm-dev at lists.llvm.org
> wrote:

> Hi all,
>
> I want to match addition with 16bit integers. So I define a pattern
> fragment as follows:
> def simm16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
>
> Now I am confused between
> (add R32:$dst, simm16:$im) and
> (add R32:$dst, (i32 simm16:$im)).
>
> Do both of them match the same pattern? Are they equivalent? If not what
> is the difference?
> I am also confused as to how ValueTypes relate to SDNodes as I think we
> are able to use both of them as nodes.
>
> --
> Regards
> Pratik Bhatu
> Dual Degree(B.Tech + M.Tech), 5th Year
> Computer Science and Engineering
> IIT Hyderabad
>
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>
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