[llvm-dev] DFAPacketizer, Scheduling and LoadLatency

[Rail Shafigulin via llvm-dev]

I'm unclear how does DFAPacketizer and the scheduler know a given
instruction is a load.
Here is what I'm talking about

Let's assume my VLIW target is described as follows:

def MyTargetItineraries :
      ProcessorItineraries<[Slot0, Slot1], [], [
        ..............................
        InstrItinData<RI, [InstrStage<1, [Slot0, Slot1]>]>,
        InstrItinData<LD, [InstrStage<1, [Slot0, Slot1]>]>, // <-- This
itinerary class describes load instructions
        InstrItinData<BR, [InstrStage<1, [Slot0]>]>
        ..............................
      ]>;

def MyTargetModel : SchedMachineModel {
  // Max issue per cycle == bundle width.
  let IssueWidth = 2;
  let Itineraries = MyTargetItineraries;
  let LoadLatency = 2;
}

Nowhere in my itinerary description it says that load instruction takes 2
cycles. In the code I couldn't find a path (but I could have missed)  how a
value from LoadLatency propagates to a load instruction? So how does the
packetzer and the scheduler know that a load instruction latency is 2
cycles?

Any help on this is appreciated.

-- 
R
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