[llvm-dev] DFAPacketizer, Scheduling and LoadLatency

Krzysztof Parzyszek via llvm-dev llvm-dev at lists.llvm.org
Tue Nov 17 03:41:15 PST 2015

On 11/16/2015 5:32 PM, Rail Shafigulin via llvm-dev wrote:
> I'm unclear how does DFAPacketizer and the scheduler know a given
> instruction is a load.
> Here is what I'm talking about
> Let's assume my VLIW target is described as follows:
> def MyTargetItineraries :
>        ProcessorItineraries<[Slot0, Slot1], [], [
>          ..............................
>          InstrItinData<RI, [InstrStage<1, [Slot0, Slot1]>]>,
>          InstrItinData<LD, [InstrStage<1, [Slot0, Slot1]>]>, // <-- This
> itinerary class describes load instructions
>          InstrItinData<BR, [InstrStage<1, [Slot0]>]>
>          ..............................
>        ]>;

As you noticed, the itinerary itself does not contain any information 
about being applicable to a load.  The connection happens through 
associating a load instruction (an instruction with a MayLoad flag) with 
this itinerary.

> def MyTargetModel : SchedMachineModel {
>    // Max issue per cycle == bundle width.
>    let IssueWidth = 2;
>    let Itineraries = MyTargetItineraries;
>    let LoadLatency = 2;
> }
> Nowhere in my itinerary description it says that load instruction takes
> 2 cycles. In the code I couldn't find a path (but I could have missed)
>   how a value from LoadLatency propagates to a load instruction? So how
> does the packetzer and the scheduler know that a load instruction
> latency is 2 cycles?
> Any help on this is appreciated.

A lot of the latency calculation is done in lib/CodeGen/TargetInstrInfo.cpp.

In particular, the LoadLatency is used in defaultDefLatency:

/// Return the default expected latency for a def based on it's opcode.
unsigned TargetInstrInfo::defaultDefLatency(
      const MCSchedModel &SchedModel, const MachineInstr *DefMI) const {
   if (DefMI->isTransient())
     return 0;
   if (DefMI->mayLoad())
     return SchedModel.LoadLatency;
   if (isHighLatencyDef(DefMI->getOpcode()))
     return SchedModel.HighLatency;
   return 1;


Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
hosted by The Linux Foundation

More information about the llvm-dev mailing list