[LLVMdev] TSFlags

[Sky Flyer]

Dear Krzysztof,

That was really much of help. I did go through the ARM code trying to
understand it.
One question that I have is, how "s" and "p" get initialized? for example
in this code that I copied from ARMInstrFormats.td


// Same as I except it can optionally modify CPSR. Note it's modeled as an
input
// operand since by default it's a zero register. It will become an
implicit def
// once it's "flipped".
class sI<dag oops, dag iops, AddrMode am, int sz,
         IndexMode im, Format f, InstrItinClass
itin,
         string opc, string asm, string
cstr,
         list<dag> pattern>
  : InstARM<am, sz, im, f, GenericDomain, cstr, itin>
{
  bits<4> p; // Predicate operand
  bits<1> s; // condition-code set flag ('1' if the insn should set the
flags)
  let Inst{31-28} =
p;

  let Inst{20} =
s;


  let OutOperandList = oops;
  let InOperandList = !con(iops, (ins pred:$p,
cc_out:$s));
  let AsmString = !strconcat(opc, "${s}${p}",
asm);
  let Pattern = pattern;
  list<Predicate> Predicates =
[IsARM];
}

The same for TSFlags; when I want to used them for condition handling, how
do they get initialized?


On Fri, Jul 10, 2015 at 5:59 PM, Krzysztof Parzyszek <
kparzysz at codeaurora.org> wrote:

> On 7/10/2015 10:23 AM, Sky Flyer wrote:
>
>> Many thanks for your prompt reply.
>>
>> I mean, imagine you have 3 bits for condition flags in your instruction
>> (e.g.  overflow, zero, carry set, ...) for conditional executions AND
>> there is no direct access to the Status Register, is it even possible to
>> implement such scenario?
>>
>>
> There doesn't have to be any explicit status register.  You can either
> create separate instructions for each condition, or have the condition as
> an extra operand.  Let's take "add" for example.  You could have several
> versions of add:
>   add     add unconditionally
>   addc    add if carry
>   addz    add if zero
>   addo    add if overflow
> and similarly for more complex conditions that your target could support,
> such as "carry or zero".  This has the disadvantage that the instruction
> set can get really large, but if the number of conditional instructions is
> small or if the possible conditions vary from one operation to another,
> this may be a viable solution.
> The other option is to model the condition as an operand (I think ARM does
> that).  So the add instruction could look like this:
>   R0 = add R1, R2, C
> where
>   C = 0: no conditions
>   C = 1: zero
>   C = 2: carry
>   C = 4: overflow
> etc.
>
> This way the instruction set would remain small, but it may involve
> special handling for it to work with the integrated assembler (if the
> native instruction format is different than what you chose).
>
> You could use the TSFlags to indicate for each instruction which condition
> this instruction can modify.  Taking the add again, it could modify all of
> the three: zero, carry and overflow, but a load could only modify zero (for
> example, specifics would depend on your target).
>
>
>
> -Krzysztof
>
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
> by The Linux Foundation
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