<div dir="ltr"><div><div>Dear Krzysztof,<br><br>That was really much of help. I did go through the ARM code trying to understand it.<br></div>One question that I have is, how "s" and "p" get initialized? for example in this code that I copied from ARMInstrFormats.td<br><br><br>// Same as I except it can optionally modify CPSR. Note it's modeled as an input <br>// operand since by default it's a zero register. It will become an implicit def <br>// once it's "flipped".<br>class sI<dag oops, dag iops, AddrMode am, int sz,<br> IndexMode im, Format f, InstrItinClass itin, <br> string opc, string asm, string cstr, <br> list<dag> pattern><br> : InstARM<am, sz, im, f, GenericDomain, cstr, itin> { <br> bits<4> p; // Predicate operand<br> bits<1> s; // condition-code set flag ('1' if the insn should set the flags) <br> let Inst{31-28} = p; <br> let Inst{20} = s; <br> <br> let OutOperandList = oops;<br> let InOperandList = !con(iops, (ins pred:$p, cc_out:$s)); <br> let AsmString = !strconcat(opc, "${s}${p}", asm); <br> let Pattern = pattern;<br> list<Predicate> Predicates = [IsARM]; <br>}<br><br></div>The same for TSFlags; when I want to used them for condition handling, how do they get initialized?<br><div><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Jul 10, 2015 at 5:59 PM, Krzysztof Parzyszek <span dir="ltr"><<a href="mailto:kparzysz@codeaurora.org" target="_blank">kparzysz@codeaurora.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="">On 7/10/2015 10:23 AM, Sky Flyer wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Many thanks for your prompt reply.<br>
<br>
I mean, imagine you have 3 bits for condition flags in your instruction<br>
(e.g. overflow, zero, carry set, ...) for conditional executions AND<br>
there is no direct access to the Status Register, is it even possible to<br>
implement such scenario?<br>
<br>
</blockquote>
<br></span>
There doesn't have to be any explicit status register. You can either create separate instructions for each condition, or have the condition as an extra operand. Let's take "add" for example. You could have several versions of add:<br>
add add unconditionally<br>
addc add if carry<br>
addz add if zero<br>
addo add if overflow<br>
and similarly for more complex conditions that your target could support, such as "carry or zero". This has the disadvantage that the instruction set can get really large, but if the number of conditional instructions is small or if the possible conditions vary from one operation to another, this may be a viable solution.<br>
The other option is to model the condition as an operand (I think ARM does that). So the add instruction could look like this:<br>
R0 = add R1, R2, C<br>
where<br>
C = 0: no conditions<br>
C = 1: zero<br>
C = 2: carry<br>
C = 4: overflow<br>
etc.<br>
<br>
This way the instruction set would remain small, but it may involve special handling for it to work with the integrated assembler (if the native instruction format is different than what you chose).<br>
<br>
You could use the TSFlags to indicate for each instruction which condition this instruction can modify. Taking the add again, it could modify all of the three: zero, carry and overflow, but a load could only modify zero (for example, specifics would depend on your target).<div class="HOEnZb"><div class="h5"><br>
<br>
<br>
-Krzysztof<br>
<br>
<br>
-- <br>
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