[LLVMdev] TSFlags

[Krzysztof Parzyszek]

On 7/10/2015 10:23 AM, Sky Flyer wrote:
> Many thanks for your prompt reply.
>
> I mean, imagine you have 3 bits for condition flags in your instruction
> (e.g.  overflow, zero, carry set, ...) for conditional executions AND
> there is no direct access to the Status Register, is it even possible to
> implement such scenario?
>

There doesn't have to be any explicit status register.  You can either 
create separate instructions for each condition, or have the condition 
as an extra operand.  Let's take "add" for example.  You could have 
several versions of add:
   add     add unconditionally
   addc    add if carry
   addz    add if zero
   addo    add if overflow
and similarly for more complex conditions that your target could 
support, such as "carry or zero".  This has the disadvantage that the 
instruction set can get really large, but if the number of conditional 
instructions is small or if the possible conditions vary from one 
operation to another, this may be a viable solution.
The other option is to model the condition as an operand (I think ARM 
does that).  So the add instruction could look like this:
   R0 = add R1, R2, C
where
   C = 0: no conditions
   C = 1: zero
   C = 2: carry
   C = 4: overflow
etc.

This way the instruction set would remain small, but it may involve 
special handling for it to work with the integrated assembler (if the 
native instruction format is different than what you chose).

You could use the TSFlags to indicate for each instruction which 
condition this instruction can modify.  Taking the add again, it could 
modify all of the three: zero, carry and overflow, but a load could only 
modify zero (for example, specifics would depend on your target).


-Krzysztof


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