[LLVMdev] New backend help request.

[David Chisnall]

On 9 Jul 2015, at 10:41, James Boulton <eiconic at googlemail.com> wrote:
> 
> I'm trying to figure out how to map more complex CISC instructions now. For
> example on the 68000, you have things like --
> 
> add.w (a0)+,(a1)+
> 
> So that equates to:
> 
> temp1 = load a0
> add 2, a0
> temp2 = load a1
> temp1 = add temp1, temp2
> store temp1, a1
> add 2, a1
> 
> How do I express that in a form for LLVM?

The simple answer is: not very easily.  I’d be inclined to treat instructions like these as optimisations and ignore them (aside from integrated assembler support) until the rest of the back end is working.  Once that’s working, take a look at how the ARM back end uses ldm and stm instructions - basically pattern matching on the MachineInstrs after code generation to fold them together.

Your other alternative in this case is to model this as an instruction that does a gather load of a two-element vector and then two extract elements.  You might be able to get the vectoriser to generate these sequences and then match them, but I suspect that you’ll then have to define a load of pseudos for vector ops (type legalisation happens before instruction selection, so it’s difficult to have types that are only valid for a few complex IR / DAG sequences).

David