[LLVMdev] New backend help request.

[Renato Golin]

On 9 July 2015 at 10:58, David Chisnall <David.Chisnall at cl.cam.ac.uk> wrote:
> The simple answer is: not very easily.  I’d be inclined to treat instructions like these as optimisations and ignore them (aside from integrated assembler support) until the rest of the back end is working.  Once that’s working, take a look at how the ARM back end uses ldm and stm instructions - basically pattern matching on the MachineInstrs after code generation to fold them together.

If you want to match the expanded pattern and merge into an add.w,
then you can use table-gen pseudo instruction patterns. If the pattern
is not simple enough, or generally comes in a random sequence, or
needs additional checks (for example, "store t1, a1" must come
*before* "add 2,a1" but "add 2,a0" can come at any time after "load
a0"), you can do like ARM's LoadStoreOptimizer and fold it after
instruction selection.


> Your other alternative in this case is to model this as an instruction that does a gather load of a two-element vector and then two extract elements.  You might be able to get the vectoriser to generate these sequences and then match them, but I suspect that you’ll then have to define a load of pseudos for vector ops (type legalisation happens before instruction selection, so it’s difficult to have types that are only valid for a few complex IR / DAG sequences).

Yeah, you'll end up with a huge and complex list of pseudos that could
bite you in the rear if you're not careful.

--renato