[LLVMdev] New backend help request.

[James Boulton]

I'm trying to figure out how to map more complex CISC instructions now. For
example on the 68000, you have things like --

add.w (a0)+,(a1)+

So that equates to:

temp1 = load a0
add 2, a0
temp2 = load a1
temp1 = add temp1, temp2
store temp1, a1
add 2, a1

How do I express that in a form for LLVM?

I see things like pre_store and post_store, but I cant find anything in the
way of documentation about this. And there doesn't appear to be a pre_load
and post_load matching pair or anything like that...

Thanks!