[LLVMdev] At which point application vs target machine type width splitting happens?

[Paul Sokolovsky]

Hello,

On Fri, 22 Feb 2013 16:50:39 +0400
Anton Korobeynikov <anton at korobeynikov.info> wrote:

> Hello
> 
> > I'm trying to understand how fitting source integer type width into
> > target machine register width happens. My reading on LLVM
> > codegeneration topics (few megabytes) so far didn't have this topic
> > mentioned explicitly.
> This is done during DAG Legalization phase. The operation is splitted
> into two (ADD + ADDC / ADDE). These DAG nodes are later matches during
> instruction selection.

Thanks for all the replies! Taking the hints, here's more datailed
flow for the "%1 = add nsw i32 %b, %a" example if someone later will
google for it:

Source file is LegalizeIntegerTypes.cpp,
DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo).
handles width splitting (which apparently in LLVM slang called
"expanding" which I'm, as a novice, find confusing).

For add/sub, this calls 
DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, SDValue &Lo, SDValue
&Hi) which splits value operation into 2 equal by width parts. If
original type is not power-of-2, it appears to be promoted first to
power-of-2 (elsewhere). For longer values, the process of splitting
applies recursively. There doesn't appear to be artificial limits on
operatable width of integer types, for example, msp430 happily adds
i128 values (with awful optimization though, like spilling values having
backing store instead of rematerializing them).

To trace thru "expand" operations, undocumented (?) -debug switch can be
passed to llc. 


-- 
Best regards,
 Paul                          mailto:pmiscml at gmail.com