[LLVMdev] At which point application vs target machine type width splitting happens?

[Anton Korobeynikov]

Hello

> I'm trying to understand how fitting source integer type width into
> target machine register width happens. My reading on LLVM
> codegeneration topics (few megabytes) so far didn't have this topic
> mentioned explicitly.
This is done during DAG Legalization phase. The operation is splitted
into two (ADD + ADDC / ADDE). These DAG nodes are later matches during
instruction selection.

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University