[LLVMdev] At which point application vs target machine type width splitting happens?

[Eli Bendersky]

On Fri, Feb 22, 2013 at 11:33 AM, Paul Sokolovsky <pmiscml at gmail.com> wrote:
> Hello,
>
> On Fri, 22 Feb 2013 16:50:39 +0400
> Anton Korobeynikov <anton at korobeynikov.info> wrote:
>
>> Hello
>>
>> > I'm trying to understand how fitting source integer type width into
>> > target machine register width happens. My reading on LLVM
>> > codegeneration topics (few megabytes) so far didn't have this topic
>> > mentioned explicitly.
>> This is done during DAG Legalization phase. The operation is splitted
>> into two (ADD + ADDC / ADDE). These DAG nodes are later matches during
>> instruction selection.
>
> Thanks for all the replies! Taking the hints, here's more datailed
> flow for the "%1 = add nsw i32 %b, %a" example if someone later will
> google for it:
>
> Source file is LegalizeIntegerTypes.cpp,
> DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo).
> handles width splitting (which apparently in LLVM slang called
> "expanding" which I'm, as a novice, find confusing).

The codegen document (http://llvm.org/docs/CodeGenerator.html) explains it:

"
There are two main ways of converting values of unsupported scalar
types to values of supported types: converting small types to larger
types (“promoting”), and breaking up large integer types into smaller
ones (“expanding”). For example, a target might require that all f32
values are promoted to f64 and that all i1/i8/i16 values are promoted
to i32. The same target might require that all i64 values be expanded
into pairs of i32 values. These changes can insert sign and zero
extensions as needed to make sure that the final code has the same
behavior as the input.
"

Eli