[LLVMdev] Predicate registers/condition codes question

[Sebastian Pop]

On Thu, May 24, 2012 at 5:40 PM, Sebastian Pop <spop at codeaurora.org> wrote:
> On Thu, May 24, 2012 at 5:06 PM, Hal Finkel <hfinkel at anl.gov> wrote:
>> Sebastian,
>>
>> First, it might be useful to look at what is done in the PowerPC
>> backend. PPC also has condition registers that are larger than the
>> 1-bit conditional results, and it defines 1-bit subregisters in
>> addition to the larger condition registers. The spill-restore code ends
>> up being more complicated, but that, perhaps, is a separate issue. [To
>> be clear, I am not advocating for (or against) this solution even if it
>> would work for you].
>
> Ok, thanks for the pointer, I'll go read in the PPC bits.

I see that PPC has its condition registers CRRC as i32, and that PPC
also has general purpose i32 registers GPRC, so the situation is slightly
different than on Hexagon, where there are no general purpose registers
of the same size as the predicate registers: i8.

So on PPC it is "safe" to promote from i1 to i32 and to "allow confusion"
between the promoted i32 and the existing operations that were using i32:
as we can always select between a CR and a GPR following the op type.

On Hexagon, if type legalization promotes i1 into i8, that would create
this confusion between the i8 ops existing before legalization and the
newly promoted ones.  Then as Ivan was suggesting, we will have to
provide custom expansion to promote the "illegal" ops on i8 on almost
all the operations, except logical ops.

Sebastian
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