[LLVMdev] Predicate registers/condition codes question

[Sebastian Pop]

On Fri, May 25, 2012 at 11:54 AM, Sebastian Pop <spop at codeaurora.org> wrote:
> On Hexagon, if type legalization promotes i1 into i8, that would create
> this confusion between the i8 ops existing before legalization and the
> newly promoted ones.  Then as Ivan was suggesting, we will have to
> provide custom expansion to promote the "illegal" ops on i8 on almost
> all the operations, except logical ops.

For reference, I just found out that adding a p8 type creates too many
problems in the generic code of LLVM: for instance, here is the last fail

 include/llvm/Target/TargetLowering.h:473:
llvm::TargetLowering::LegalizeAction
llvm::TargetLowering::getCondCodeAction(llvm::ISD::CondCode,
llvm::EVT) const: Assertion `(unsigned)CC <
array_lengthof(CondCodeActions) && (unsigned)VT.getSimpleVT().SimpleTy
< sizeof(CondCodeActions[0])*4 && "Table isn't big enough!"' failed.

that looks like we would have to add some more space in a cond code
table, and we would have to specify how to handle p8 types in conditions.

I will thus use the i8 type for predicates in Hexagon, and I will deal with
the difficulties I mentioned in my previous email.

Sebastian
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