[LLVMdev] Predicate registers/condition codes question

[Sebastian Pop]

Hi Ivan,

On Thu, May 24, 2012 at 6:43 PM, Ivan Llopard <ivanllopard at gmail.com> wrote:
> Just an idea, you may know that it's possible to custom expand
> operations with illegal types and it might be useful in this case
> (considering i1 as illegal). The TypeLegalizer will callback to your
> lowering function at the very beginning of the Combining/Legalization
> phases. If you add HexagonISD nodes in the process while promoting
> operands/result, you will be able to precisely match them later with its
> associated regclass (PReg?).
> Unfortunately, it will not resolve your problem with non-allowed ops for
> i8 types and I think I'm missing something regarding this matter. Why
> don't you mark for promotion everything but logical ops ?

I will try this, although I think it will be painful to maintain an up
to date list
of ops marked for promotion.

I was hoping to find a way to implement the opposite: specify that the
few logical ops are legal on i8, and the default action on the rest of
opcodes would be to promote to i32.

Another way that would be practical is to "remember" that an i8 type
is the result of a first promotion from i1: that would be a legal i8, and
an i8 type that has not been already promoted is illegal and has to
be promoted to i32.  The only way I found to implement this is with a
different type: p8.

> Are copies between pred regs and IntRegs not allowed ?

Copies between pred and int registers are allowed in Hexagon.

Sebastian
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