[LLVMdev] Predicate registers/condition codes question

[Ivan Llopard]

On 25/05/2012 00:40, Sebastian Pop wrote:
> On Thu, May 24, 2012 at 5:06 PM, Hal Finkel<hfinkel at anl.gov>  wrote:
>> Sebastian,
>>
>> First, it might be useful to look at what is done in the PowerPC
>> backend. PPC also has condition registers that are larger than the
>> 1-bit conditional results, and it defines 1-bit subregisters in
>> addition to the larger condition registers. The spill-restore code ends
>> up being more complicated, but that, perhaps, is a separate issue. [To
>> be clear, I am not advocating for (or against) this solution even if it
>> would work for you].
>
> Ok, thanks for the pointer, I'll go read in the PPC bits.
>
>> Second, generically speaking, the problem that you
>> have seems much more general than the solution you propose. Correct
>> me if I'm wrong, but your fundamental issue is that you have a type, i8,
>> than can exist in different register classes, and the operations that
>> are legal on that type depend on the current register class. The reason
>> this is a problem is that legalization happens before register-class
>> assignment.
>
> Yes, that's correct.
>
>> Currently, isTypeLegal does not take an opcode parameter, but maybe
>> changing it to depend on the type of operation (like getTypeToPromoteTo
>> does) and the opcode of the node's inputs would help?
>
> I will try to see if I can fix isTypeLegal.
> Thanks for your helpful comments.

Just an idea, you may know that it's possible to custom expand 
operations with illegal types and it might be useful in this case 
(considering i1 as illegal). The TypeLegalizer will callback to your 
lowering function at the very beginning of the Combining/Legalization 
phases. If you add HexagonISD nodes in the process while promoting 
operands/result, you will be able to precisely match them later with its 
associated regclass (PReg?).
Unfortunately, it will not resolve your problem with non-allowed ops for 
i8 types and I think I'm missing something regarding this matter. Why 
don't you mark for promotion everything but logical ops ? Are copies 
between pred regs and IntRegs not allowed ?

Ivan

>
> Sebastian
> --
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