[LLVMdev] Predicate registers/condition codes question

[Sebastian Pop]

On Thu, May 24, 2012 at 5:06 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> Sebastian,
>
> First, it might be useful to look at what is done in the PowerPC
> backend. PPC also has condition registers that are larger than the
> 1-bit conditional results, and it defines 1-bit subregisters in
> addition to the larger condition registers. The spill-restore code ends
> up being more complicated, but that, perhaps, is a separate issue. [To
> be clear, I am not advocating for (or against) this solution even if it
> would work for you].

Ok, thanks for the pointer, I'll go read in the PPC bits.

> Second, generically speaking, the problem that you
> have seems much more general than the solution you propose. Correct
> me if I'm wrong, but your fundamental issue is that you have a type, i8,
> than can exist in different register classes, and the operations that
> are legal on that type depend on the current register class. The reason
> this is a problem is that legalization happens before register-class
> assignment.

Yes, that's correct.

> Currently, isTypeLegal does not take an opcode parameter, but maybe
> changing it to depend on the type of operation (like getTypeToPromoteTo
> does) and the opcode of the node's inputs would help?

I will try to see if I can fix isTypeLegal.
Thanks for your helpful comments.

Sebastian
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